TY - GEN
T1 - On using locking caches in embedded real-time systems
AU - Martí Campoy, A.
AU - Tamura, E.
AU - Sáez, S.
AU - Rodríguez, F.
AU - Busquets-Mataix, J. V.
PY - 2005
Y1 - 2005
N2 - Cache memories are crucial to obtain high performance on contemporary processors. However, they have been traditionally avoided in embedded real-time systems due to their lack of determinism. Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. This work reviews several techniques developed by the authors to use cache memories in "real" embedded real-time systems, with the ease of use in mind. Those techniques are based on a locking cache, which offers a very predictable behaviour. Both static and dynamic use are proposed as well as the algorithms and methods required to make the schedulability analysis using two different scheduling policies. Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. Finally, a set of statistical analyses compares the locking cache versus a conventional one.
AB - Cache memories are crucial to obtain high performance on contemporary processors. However, they have been traditionally avoided in embedded real-time systems due to their lack of determinism. Unfortunately, most of the techniques to attain predictability on caches are complex to apply, precluding their use on real applications. This work reviews several techniques developed by the authors to use cache memories in "real" embedded real-time systems, with the ease of use in mind. Those techniques are based on a locking cache, which offers a very predictable behaviour. Both static and dynamic use are proposed as well as the algorithms and methods required to make the schedulability analysis using two different scheduling policies. Also proposed is a genetic algorithm that finds, within acceptable computational cost, the sub-optimal set of instructions that must be preloaded in cache. Finally, a set of statistical analyses compares the locking cache versus a conventional one.
KW - Cache memories
KW - Embedded real-time systems
KW - Execution time
KW - Genetic al-gorithms
KW - Performance evaluation
KW - Predictability
KW - Response time
KW - Schedulability analysis
UR - http://www.scopus.com/inward/record.url?scp=33744940545&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:33744940545
SN - 3540308814
SN - 9783540308812
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 150
EP - 159
BT - Embedded Software and Systems
T2 - 2nd International Conference on Embedded Software and Systems, ICESS 2005
Y2 - 16 December 2005 through 18 December 2005
ER -