TY - GEN
T1 - An algorithm for deciding minimal cache sizes in real-time systems
AU - Campoy, Antonio Martí
AU - Rodríguez-Ballester, Francisco
AU - Tamura, Eugenio
AU - Ors, Rafael
PY - 2011
Y1 - 2011
N2 - When designing real-time systems, predictability is of utmost importance. A locking cache is a cache memory that allows loading and locking instructions, thus avoiding their replacement. This way, regarding memory accesses, execution time of instructions is constant since it does not depend on the sequence of memory references. With a predictable behaviour, locking cache memories are a practical alternative to conventional caches for real-time systems. Offering similar performance to conventional caches, locking caches allow an accurate yet simple schedulability analysis. Locking caches may also help to reduce the size of a system, by means of reducing cache size. When reducing cache size, also cost and power consumption may be reduced. This way, both predictability and cost saving is provided by means of locking cache. This work presents a set of algorithms, aimed to select the contents of a locking cache that provides the minimum locking cache size, while the system remains schedulable. Compared to a previous approach, the algorithms presented in this paper are able to select a set of main memory blocks that result in a smaller cache size.
AB - When designing real-time systems, predictability is of utmost importance. A locking cache is a cache memory that allows loading and locking instructions, thus avoiding their replacement. This way, regarding memory accesses, execution time of instructions is constant since it does not depend on the sequence of memory references. With a predictable behaviour, locking cache memories are a practical alternative to conventional caches for real-time systems. Offering similar performance to conventional caches, locking caches allow an accurate yet simple schedulability analysis. Locking caches may also help to reduce the size of a system, by means of reducing cache size. When reducing cache size, also cost and power consumption may be reduced. This way, both predictability and cost saving is provided by means of locking cache. This work presents a set of algorithms, aimed to select the contents of a locking cache that provides the minimum locking cache size, while the system remains schedulable. Compared to a previous approach, the algorithms presented in this paper are able to select a set of main memory blocks that result in a smaller cache size.
KW - Genetic algorithms
KW - Greedy algorithms
KW - Locking-cache memory
KW - Real-time systems
KW - Schedulability
UR - http://www.scopus.com/inward/record.url?scp=84860423637&partnerID=8YFLogxK
U2 - 10.1145/2001576.2001733
DO - 10.1145/2001576.2001733
M3 - Conference contribution
AN - SCOPUS:84860423637
SN - 9781450305570
T3 - Genetic and Evolutionary Computation Conference, GECCO'11
SP - 1163
EP - 1169
BT - Genetic and Evolutionary Computation Conference, GECCO'11
T2 - 13th Annual Genetic and Evolutionary Computation Conference, GECCO'11
Y2 - 12 July 2011 through 16 July 2011
ER -