High speed parallel arquitecture for fuzzy inference and fuzzy control of multiple processes

A hardware processing arquitecture and an associated graphical compiler for Fuzzy inference and control of multiple antecedents and output variables is presented. The hardware arquitecture, running as a Fuzzy co-processor for IBM PC (or compatible) platforms, uses as core elements the FP9000 rules chips and FP9001 defuzzifier chips proposed by Yamakawa et al. The claimed response for these processors is in the order of 0.714 μs per fuzzy inference without defuzzication, and 1.6 μs per fuzzy inference including center of gravity defuzzification. The arquitecture proposed permits fuzzy inference simulation under PC master control, as well as direct fuzzy control of output process. The system relies on the partial flexibility of the fuzzy chips (fuzzy rule parameters are programmable through a digital interface), their embedded parallel processing, and the analog processing speeds, in order to achieve high speed simulation and real-time control response. An object oriented graphical compiler designed to permit intuitive definitions and tuning of linguistic labels within membership functions, as well as plant control systems modeling, is currently under development. The compiler interacts directly with the PCs i80X86 and the Fuzzy parallel engine (in a master-slave configuration), and generates, at users request, intermediate flat ANSI C type code for portability.