Abstract
This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18µm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.
Translated title of the contribution | DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY |
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Original language | Spanish |
Pages (from-to) | 167-181 |
Number of pages | 15 |
Journal | Revista EIA |
Volume | 9 |
Issue number | 17 |
State | Published - Jul 2012 |
Keywords
- VLSI
- rail to rail operational amplifier
- CMOS