DISEÑO DE UN AMPLIFICADOR RIEL A RIEL CON TECNOLOGÍA CMOS 0,18 μm

Translated title of the contribution: DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY

Diego F. Hernández, Juan F. Antolínez, Elkin Y. Pineda, German Yamhure Kattah, Carlos Ivan Paez Rueda

Research output: Contribution to journalArticlepeer-review

Abstract

This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18µm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.
Translated title of the contributionDESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY
Original languageSpanish
Pages (from-to)167-181
Number of pages15
JournalRevista EIA
Volume9
Issue number17
StatePublished - Jul 2012

Keywords

  • VLSI
  • rail to rail operational amplifier
  • CMOS

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