Comparative analysis of threshold voltage extraction techniques based in the MOSFET gm/ID characteristic

Context: In advanced ultralow-power devices, it is necessary to use the accuracy extraction procedures of the MOSFET threshold voltage to fully characterize the devices. These procedures are based in the measurement of the Tran-conductance efficiency (gm/ID) and its first derivative in function of the voltage gate source (d(gm/ID)/dVGS). In order to increase their independency respect to the non-zero drain source voltage (VDS ≠0) it is used a process to correct the error. Theoretically, VDS should be 0 V; however, the VDS is grater than 10 mV in the experimental setup in order to avoid electrical noise, but less than a certain maximum value for allowing the MOSFET operation in the linear region of the weak inversion.

Objective: To compare the extraction procedure proposed by (MC Schneider et al., 2006) and the method proposed by (Rudenko et al., 2011) with a generic, controlled and coherent test scenario.

Method: This paper proposes a test scenario based on the Advanced Compact MOSFET model (ACM) of a long channel MOSFET made in a standard 0.35 mm CMOS process, implemented numerically in MATLABâ. The concept of Power Error Correction (PEC) was used to compare the two processes numerically; it quantifies the sensitivity of the extraction process to the effect by the non-zero voltage value of the VDS in the experimental setup (i.e., NZ-DS effect).

Results: The error correction procedure proposed by (Siebel et al., 2012, Schneider et al., 2006) estimates the NZ-DS effect better than the procedure proposed by (Rudenko et al., 2011), considering the average, maximum and minimum PEC obtained for both extraction methodologies for a long channel MOSFET fabricated in a standard CMOS process of 0.35 μm, when the VDS is less than 50 mV.

Conclusions: The Vth extraction procedure proposed by (MC Schneider et al., 2006) is more robust than the method proposed by (Rudenko et al., 2011) regarding the NZ-DS effect.